The present invention is directed to a clock supply for multiplex systems clock supply for multiplex systems having at least one clock generator for distributing at least one system clock signal and at least one frame clock signal, whereby both the system clock signal as well as the frame clock signal are supplied to at least one assembly of the multiplexer system. The term "assembly" is used herein to refer to any type of electronic circuit or module used in multiplex systems.
In addition to supplying a system clock signal (bit clock signal) to individual assemblies, it is necessary in digital multiplex systems to also supply a frame clock signal to individual assemblies in order to achieve a proper allocation of the individual data channels transmitted. In digital cross-connect multiplexer systems, for example, the digital signals are patched in a time slot-controlled switching matrix network. To this end, a frame with time slots is formed in which the digital signals are classified. The through-connection in the switching matrix network occurs synchronously, i.e. the alignment of the time slots of the various digital signals must coincide. In order to assure this, a centrally generated frame clock for the system is required. All internal digital signal frames are generated using the frame clock. At the same time, a transit time equalization between the digital signals and the frame is implemented with phase matching circuits. Due to the spatial spread of the assemblies (function units), the problem occurs of bridging the existing distances without transit time dislocations between the system clocks and frame clocks, particularly in systems having high switching capacity. The transit times of the amplifiers and lines are no longer negligible for high bit rates. These difficulties are increased when a switching from a working clock supply to a standby clock supply with clock lines that are separately conducted for security reasons. In the prior art the system clock line and the frame clock line were conducted strictly in parallel with identical line lengths in order to obtain identical transit times.
For higher bit rates and/or long line lengths, this method, however, does not provide any assurance against undesired transit dislocation because of tolerance variations of the necessary intermediate repeaters and of the connecting cables.